* Description
* Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times
* Asynchronous Reset
* Complementary Outputs
* Buffered Inputs
* TTAyp=ic2a5lofCMAX = 60MHz at VCC = 5V, CL = 15pF,
* Fanout (Over Temperatur
CD74HC73 Datasheet (972.13 KB)
CD74HC73
972.13 KB
Dual j-k flip-flop.
Data sheet acquired from Harris Semiconductor SCHS134E
February 1998 - Revised September 2003
CD54HC73, CD74HC73, CD74HCT73
Dual J-K Flip-Flop with R.
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