CY74FCT16500T - 18-Bit Registered Transceivers
These 18-bit universal bus transceivers can be operated in transparent, latched, or clock modes by combining D-type latches and D-type flip-flops.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock inputs (CLKAB and CLKBA) inputs.
For A-t
CY74FCT16500T Features
* FCT-C speed at 4.6 ns
* Ioff supports partial-power- mode operation
* Edge-rate control circuitry for significantly improved noise characteristics
* Typical output skew < 250 ps
* ESD > 2000V
* TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages
