SN54LV10A - TRIPLE 3-INPUT POSITIVE-NAND GATE
ordering information These triple 3-input positive-NAND gates are designed for 2-V to 5.5-V VCC operation.
The ’LV10A devices perform the Boolean function Y = A * B * C or Y = A + B + C in positive logic.
These devices are fully specified for partial-power-down applications using Iof
SN54LV10A, SN74LV10A TRIPLE 3ĆINPUT POSITIVEĆNAND GATE D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charg
