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SN74ALVCH16524 - 18-BIT REGISTERED BUS TRANSCEIVER

Datasheet Summary

Description

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs.

For the A-to-B data flow, the data flows through a single buffer.

Features

  • Member of the Texas Instruments Widebus™ Family.
  • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode.
  • Operates From 1.65 V to 3.6 V.
  • Max tpd of 3.2 ns at 3.3 V.
  • ±24-mA Output Drive at 3.3 V.
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors.
  • Latch-Up Performance Exceeds 250 mA Per JESD 17.
  • ESD Performance Tested.

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Datasheet preview – SN74ALVCH16524

Datasheet Details

Part number SN74ALVCH16524
Manufacturer Texas Instruments
File Size 247.11 KB
Description 18-BIT REGISTERED BUS TRANSCEIVER
Datasheet download datasheet SN74ALVCH16524 Datasheet
Additional preview pages of the SN74ALVCH16524 datasheet.

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Full PDF Text Transcription

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www.ti.com FEATURES • Member of the Texas Instruments Widebus™ Family • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enable Mode • Operates From 1.65 V to 3.6 V • Max tpd of 3.2 ns at 3.3 V • ±24-mA Output Drive at 3.3 V • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) DESCRIPTION/ORDERING INFORMATION This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA) and clock-enable (CLKENBA) inputs.
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