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SN74AUC125 QUADRUPLE BUS BUFFER GATE

SN74AUC125 Description

www.ti.com .
ORDERING INFORMATION This quadruple bus buffer gate is designed for 0.

SN74AUC125 Features

* Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
* Ioff Supports Partial-Power-Down Mode Operation
* Sub-1-V Operable
* Max tpd of 2.1 ns at 1.8 V
* Low Power Consumption, 10-µA Max ICC
* ±8-mA Output Dri

SN74AUC125 Applications

* using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. TA
* 40°C to 85°C QFN
* RGY ORDERING INFORMATION PACKAGE (1) ORDERABLE PART NUMBER Tape and reel SN74AUC125RGYR TOP-SIDE MARKING MS125 (1) Pac

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QUADRUPLE BUS BUFFER GATE Texas Instruments
Texas Instruments SN74AUC125-like datasheet