SN74AUC125 Datasheet, Gate, Texas Instruments

SN74AUC125 Features

• Gate
• Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Ioff Supports Partial-Power-Down Mode Operation
• Sub-1-V Oper

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Part number:

SN74AUC125

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Texas Instruments ↗

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📄 Datasheet

Description:

Quadruple bus buffer gate. ORDERING INFORMATION This quadruple bus buffer gate is designed for 0.8-V to 2.7-V VCC operation, but is designed specifically for 1.

SN74AUC125 Application

• Applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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SN74AUC125

Texas Instruments

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