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SN74AUC126 QUADRUPLE BUS BUFFER GATE

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Description

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ORDERING INFORMATION This quadruple bus buffer gate is designed for 0.

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Features

* Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
* Ioff Supports Partial-Power-Down Mode Operation
* Sub 1-V Operable
* Max tpd of 2.1 ns at 1.8 V
* Low Power Consumption, 10-µA Max ICC
* ±8-mA Output Dri

Applications

* using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION TA
* 40°C to 85°C QFN
* RGY PACKAGE (1) Tape and reel ORDERABLE PART NUMBER SN74AUC126RGYR TOP-SIDE MARKING MS126 (1) Packa

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