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SN74AUC2G126 DUAL BUS BUFFER GATE

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Description

www.ti.com SN74AUC2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS SCES533C * DECEMBER 2003 * REVISED JANUARY 2007 .
ORDERING INFORMATION This dual bus buffer gate is operational at 0.

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Features

* Available in the Texas Instruments NanoFreeā„¢ Package
* Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
* Ioff Supports Partial-Power-Down Mode Operation
* Sub-1-V Operable
* Max tpd of 1.9 ns at 1.8 V

Applications

* using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, li

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