* a common clock enable instead of a common clear. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if CLKEN is low. Clock triggering occurs at a particular voltage level and is not directly related to
SN74F378 Datasheet (187.57 KB)
SN74F378
187.57 KB
Hex d-type flip-flop.
* Contains Six D-Type Flip-Flops
With Single-Rail Outputs
* Applications Include:
Buffer/Storage Registers
Shift Registers
Pattern Gen.
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