* a latched clock enable (CE) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if CE is low. Clock triggering occurs at a particular voltage level and is not directly related to the positive-goin
SN74F377AN Datasheet (838.12 KB)
SN74F377AN
838.12 KB
Octal d-type flip-flop.
* Contains Eight D-Type Flip-Flops
With Single-Rail Outputs
* Clock Enable Latched to Avoid False
Clocking
* Applications Incl.
📁 Related Datasheet
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