* 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are s
SN74LV374A-EP Datasheet (693.97 KB)
SN74LV374A-EP
693.97 KB
Octal edge-triggered d-type flip-flop.
SN74LV374AĆEP OCTAL EDGEĆTRIGGERED DĆTYPE FLIPĆFLOP WITH 3ĆSTATE OUTPUTS SCLS500A MAY 2003 REVISED MAY 2004 D Controlled Baseline.
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