Datasheet4U Logo Datasheet4U.com

SN74LVTH125-EP 3.3-V ABT QUADRUPLE BUS BUFFER

SN74LVTH125-EP Description

D Controlled Baseline * One Assembly/Test Site, One Fabrication Site D Enhanced Diminishing Manufacturing Sources (DMS) Support D Enhanced Pro.
ordering information This bus buffer is designed specifically for low-voltage (3.

SN74LVTH125-EP Features

* independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not rec

SN74LVTH125-EP Applications

* using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. OR

📥 Download Datasheet

Preview of SN74LVTH125-EP PDF
datasheet Preview Page 2 datasheet Preview Page 3

📁 Related Datasheet

  • SN74LVC1G125 - high performance non-inverting buffer (UMW)
  • SN74LVC1G34 - Single buffer (UMW)
  • SN74L71 - AND-Gate R-S Master-Slave F-F (National Semiconductor)
  • SN74L74N - Dual D-Type Flip-Flop (ETC)
  • SN74LS00 - QUAD 2-INPUT NAND GATE (Motorola)
  • SN74LS02 - QUAD 2-INPUT NOR GATE (Motorola)
  • SN74LS04 - Hex Inverter (ON Semiconductor)
  • SN74LS04D - Hex Inverter (ON Semiconductor)

📌 All Tags

3.3-V ABT QUADRUPLE BUS BUFFER Texas Instruments
Texas Instruments SN74LVTH125-EP-like datasheet