N9H20K11N Datasheet | Nuvoton Technology

N9H20 ARM® ARM926EJ-S Based 32-bit Microprocessor N9H20 Series Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of ARM926EJ-S based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. .nuvoton. N9H20 SERIES DATASHEET Nov. 18, 2021 Page 1 of 58 Rev 1.25 N9H20 1 GENERAL DESCRIPTION The N9H20 series is built on the ARM926EJ-S, synchronous DRAM, 2D Bit BLT accelerator, LCD panel interface, USB 1.1 Host & USB2.0 HS Device core and integrated with JPEG codec, 32-channel SPU (Sound Processing Unit), ADC, DAC, for meeting various kinds of application needs for saving the BOM cost and makes the best choice for LCD application of cost/performance products. Maximum resolution is XVGA (1,024x768)@TFT LCD panel. The 2D Bit BLT accelerator accelerates the graphic putation to make the rendering smooth and off-load CPU to save power consumption. The open source code environment provides the product development more flexibility. For reducing system plexity while cutting the BOM cost, the N9H20 series provides MCP (Multi-Chip Package) to ensure higher performance and to minimize the system design efforts. Total BOM cost could be cut by employing 2-layer PCB along with the elimination of external parts, EMI prevention ponents and saving board design space. 1.1 Applications - HMI - Home Appliance - Advertisement N9H20 SERIES DATASHEET Nov. 18, 2021 Page 7 of 58 Rev 1.25 N9H20 2 Features - CPU - ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache - Frequency up to 200MHz@1.8V or 240MHz@2.0V core power operation voltage - JTAG interface supported for development and debugging -...