N9H20K51N Datasheet | Nuvoton Technology

DESCRIPTION The N9H20 series is built on the ARM926EJ-S, synchronous DRAM, 2D Bit BLT accelerator, LCD panel interface, USB 1.1 Host & USB2.0 HS Device core and integrated with JPEG codec, 32-channel SPU (Sound Processing Unit), ADC, DAC, for meeting various kinds of application needs for saving the BOM cost and makes the best choice for LCD application of cost/performance products. Maximum resolution is XVGA (1,024x768)@TFT LCD panel. The 2D Bit BLT accelerator accelerates the graphic putation to make the rendering smooth and off-load CPU to save power consumption. The open source code environment provides the product development more flexibility. For reducing system plexity while cutting the BOM cost, the N9H20 series provides MCP (Multi-Chip Package) to ensure higher performance and to minimize the system design efforts. Total BOM cost could be cut by employing 2-layer PCB along with the elimination of external parts, EMI prevention ponents and saving board design space. 1.1 Applications - HMI - Home Appliance - Advertisement N9H20 SERIES DATASHEET Nov. 18, 2021 Page 7 of 58 Rev 1.25 N9H20 2 FEATURES - CPU - ARM926EJ-S 32-bit RISC CPU with 8KB I-Cache & 8KB D-Cache - Frequency up to 200MHz@1.8V or 240MHz@2.0V core power operation voltage - JTAG interface supported for development and debugging - Internal SRAM & ROM - 8KB internal SRAM and 16KB IBR internal booting ROM supported - IBR booting messages displayed by UART console for debugging supported - Different system booting modes supported: - Memory card - SD card or e MMC Flash device - SD-to-NAND flash bridge - Raw NAND Flash - SPI Flash - USB - EDMA (Enhanced DMA) - Totally 5 DMA channels supported - 4 peripheral DMA channels for transfer between memory and on-chip peripherals, such as ADC, UART and SPI - One dedicated channel for memory-to-memory transfer - Byte, half-word and word data width types supported - Single and burst transfer modes supported - Block transfer supported in memory-to-memory...