ADS6616A4A Description
The ADS6616A4A are four-bank Synchronous DRAMs organized as 1,048,576 words x 16 bits x 4 banks, Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth high performance memory system...
ADS6616A4A Key Features
- JEDEC standard LVTTL 3.3V power supply -MRS Cycle with address key programs