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S2042 - (S2042 / S2043) HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS

General Description

S2042/S2043 S2042/S2043

Key Features

  • Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards.
  • S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference.
  • S2043 receiver PLL configured for clock and data recovery.
  • 1062, 531 and 266 Mb/s operation.
  • 10- or 20-bit parallel TTL compatible interface.
  • 1 watt typical power dissipation for chipset.
  • +3.3/+5V power supply.
  • Low-jitter.

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Datasheet Details

Part number S2042
Manufacturer AMCC
File Size 211.04 KB
Description (S2042 / S2043) HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Datasheet download datasheet S2042 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com PRELIMINARY DEVICE SPECIFICATION ® HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS BiCMOS PECL CLOCK SERIAL GENERATOR HIGH PERFORMANCE INTERFACE CIRCUITS GENERAL DESCRIPTION S2042/S2043 S2042/S2043 FEATURES • Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards • S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference • S2043 receiver PLL configured for clock and data recovery • 1062, 531 and 266 Mb/s operation • 10- or 20-bit parallel TTL compatible interface • 1 watt typical power dissipation for chipset • +3.