AMCC S2052
The S2052 transmitter and receiver chip is designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces conforming to the requirements of the ANSI X3T11 Fibre Channel specification. The chip runs at 1250.0, and 1062.5 Mbit/s data rates with associated 10-bit data word. The chip performs parallel-to-serial and serial-to-parallel conversion and framing for block-encoded data.| Part No. | S2052 |
|---|---|
| Datasheet | S2052 Download |
| Manufacturer | AMCC |
| Description | FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER |
| Buy | Stock & Price |
FEATURES
● Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards and IEEE 802.3Z Gigabit EthernetAPPLICATIONS
● Transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference● Receiver PLL configured for clock and data recovery
● 1250 and 1062 Mb/s operation
● 10-bit parallel TTL compatible interface
● 800mW typical power dissipation
● +3.3V power supply
● Low-jitter serial PECL compatible interface
● Lock detect
● Local loopback
● 64 PQFP package
● Fibre Channel framing performed by receiver
● Continuous downstream clocking from receiver
● Drives 30m of Twinax cable directly
APPLICATIONS
High-speed data communications● Workstation
● Frame buffer
● Switched networks
● Data broadcast environments
● Proprietary extended backplanes
● RAID drives
● Mass storage devices
GENERAL DESCRIPTION
The transmitter’s on-chip PLL synthesizes the highspeed clock from a low-speed reference. The receiver’s on-chip PLL synchronizes directly to incoming digital signal to receive the data stream.
