S5933QE - PCI Interface Device Summary

General Description

When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasserts FRAME# on the next clock to indicate the last data phase is in progress.

📥 Download Datasheet

S5933QE pci interface device summary by AMCC - Datasheet Preview

Datasheet Details

Part number	S5933QE
Manufacturer	AMCC
File Size	125.58 KB
Description	PCI Interface Device Summary
Datasheet	S5933QE Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
S5933QE	Controller Device Summary	ETC
S5930	NMOS multichannel detector head	Hamamatsu Corporation
S5930-256S	NMOS multichannel detector head	Hamamatsu Corporation
S5930-512S	NMOS multichannel detector head	Hamamatsu Corporation
S5931	NMOS multichannel detector head	Hamamatsu Corporation

Other Datasheets by AMCC

Part Number	Description
S5933	32-Bit PCI MatchMaker
S5935	32-Bit Pci Bus Master/target

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

www.DataSheet4U.com PCI Interface Device Summary S5933QE Revision 4 January 6, 1999 Factory Device Update The following are all known device and document errors for the AMCC S5933 PCI Matchmaker revision QE and the 1998 device data book. The workarounds described below are factory suggestions and are not to imply the only or all possible solutions. Contact your local Field Application Engineer for new workaround developements. Also contact your AMCC FAE or local Insight Technical Sales Engineer for the latest design notes and data book corrections or see the AMCC home page at www.amcc.com.