DESCRIPTION
: When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, If another value is written from the add-on at the right moment, an internal condition may cause IRDY# to remain asserted to sustain the burst, but FRAME# has already been deasserted. Workaround: Externally synchronizing WRFIFO# or WR# to BPCLK moves the rising edge of the write strobe to prevent this event from occurring. Request separate D8 applications note from your local FAE or Insight TSE for more detail. Status: No factory plan to re-spin. D14.1: False Add-On to PCI FIFO Empty Indication DESCRIPTION
: If the last data in the Add-On to PCI FIFO is written by the S5933 to the PCI bus and receives a target retry, the FWE output and Add-On to PCI FIFO status bits will go active, indicating that the FIFO is empty, even though the final data has not yet been transferred. This is only a problem when using Add-On initiated bus mastering when FWE is used as a condition to deassert AMWEN at the end of a bus master write.
