S5933QE Overview
When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasserts FRAME# on the next clock to indicate the last data phase is in progress. If another value is written from the add-on at the right moment, an internal condition may cause IRDY# to remain asserted to sustain the burst, but FRAME# has already been deasserted. Externally synchronizing WRFIFO# or WR# to...