AM29BDS640G Datasheet | AMD

Feature - Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VIO pin - 1.8V and 3V patible I/O signals - Simultaneous Read/Write operation - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations - Four bank architecture: 16Mb/16Mb/16Mb/16Mb - Programmable Burst Interface - 2 Modes of Burst Read Operation - Linear Burst: 8, 16, and 32 words with wrap-around - Continuous Sequential Burst - Sector Architecture - Eight 8 Kword sectors and one hundred twenty-six 32 Kword sectors - Banks A and D each contain four 8 Kword sectors and thirty-one 32 Kword sectors; Banks B and C each contain thirty-two 32 Kword sectors - Eight 8 Kword boot sectors, four at the top of the address range, and four at the bottom of the address range - Minimum 1 million erase cycle guarantee per sector - 20-year data retention at 125°C - Reliable operation for the life of the system - 80-ball FBGA package - - - - Burst Mode Read: 10 m A Simultaneous Operation: 25 m A Program/Erase: 15 m A Standby mode: 0.2 µA HARDWARE FEATURES - Sector Protection - Software mand sector locking - Reduced Wait-State Handshaking feature available - Provides host system with minimum possible latency by monitoring RDY - Hardware reset input (RESET#) - Hardware method to reset the device for reading array data - WP# input - Write protect (WP#) function protects sectors 0 and 1 (bottom boot), or sectors 132...