GENERAL DESCRIPTION
AMD PRELIMINARY BLOCK DIAGRAM Am486 CPU Pipelined 32-Bit Microarchitecture VOLDET 64-Bit Interunit Transfer Bus 32-Bit Data Bus 32 32-Bit Data Bus 32 Linear Address Bus Base/ Index Bus 32 ALU 32 PCD, PWT Segmentation Unit Descriptor Registers Limit and Attribute PLA 2 Paging Unit 20 Physical Address 8-Kbyte Cache Cache Unit 32 32 Core Clock Power Planes VCC, VSS CLKMUL Clock Multiplier CLK Barrel Shifter Register File Address Drivers Bus Interface A31−A2, BE3−BE0 Write Buffers 4 x 80 Data Bus Transceivers D31−D0 ADS, W/R, D/C, M/IO, PCD, PWT, RDY, LOCK, PLOCK, BOFF, A20M, BREQ, HOLD, HLDA, RESET, INTR, NMI, FERR, IGNNE, UP Translation Lookaside Buffer 32 128 Bus Control Request Sequencer Micro-instruction Displacement Bus 32 Code Stream Prefetcher 32-byte Code Queue 2 x 16 bytes FloatingPoint Unit FloatingPoint Register File Central and Protection Test Unit Decoded Instruction Path Burst Bus Control Bus Size Control Cache Control Parity Generation and Control Bounda...
AMD
