Am91L12 Datasheet | AMD

DESCRIPTION The Am9112/Am91 L 12 series of products are high performance, low power, 1024-bit, static read/write random access memories. They offer a range of speeds and power dissipations including versions as fast as 200ns and as low as 1OOm W typical. Each memory is implemented as 256 words by 4-bits per word. This organization allows efficient design of small memory systems and permits finer resolution of incremental memory word size relative to 1024 by 1 devices. The output and input data signals are internally bussed together and share 4 mon I/O pins. This feature keeps the package size small and provides a simplified interface to bus-oriented systems. The Am9112/Am91 L 12 memories may be operated in a DC standby mode for reductions of as much as 84% of the normal operating power dissipation. Though the memory cannot be operated, data can be retained in the storage cells with a power supply as low as 1.5 volts. The Am91 L12 versions offer reduced power during normal operating conditions as well as even lower dissipation in standby mode. The eight Address inputs are decoded to select 1-of-256 locations within the memory. The Chip Enable input acts as a high-order address in multiple chip systems. It also controls the write amplifier and the output buffers in conjunction with the Write Enable input. When CE is low and WE is high, the write amplifiers are disabled, the output buffers are enabled and the memory will execute a read cycle. When CE is low and WE is low, the write amplifiers are enabled, the. output buffers are disabled and the memory will execute a write cycle. When CE is high both the write amplifiers and the output buffers are disabled. These memories are fully static and require no refresh operations or sense amplifiers or clocks. All input and output voltage levels are identical to standard TTL specifications, including the power supply. CONNECTION...