Am91L30 Datasheet | AMD

DESCRIPTION The Am9130 and Am91 L30 products are high performance, adaptive, low-power, 4k-bit, static, read/write random access memories. They are implemented as 1024 words by 4 bits per word. Only a single +5V power supply is required for normal operation. A DC power-down mode reduces power while retaining data with a supply voltage as low as 1.5V. All interface signal levels are identical to TTL specifications, providing good noise immunity and simplified system design. All inputs are purely capacitive MOS loads. The outputs will drive two full TIL loads or more than eight low-power Schottky loads. Operational cycles are initiated when the Chip Enable clock goes HIGH. When the read or write is plete, Chip Enable goes LOW to preset the memory for the next cycle. Address and Chip Select signals are latched on-chip to simplify system timing. Output data is also latched and is available until the next operating cycle. The WE signal is HIGH for all read operations and is LOW during the Chip Enable time to perform a write. Data In and Data Out signals share mon I/O pins. Memory Status is an output signal that indicates when data is actually valid and when the preset interval is plete. It can be used to generate the CE input and to improve the memory performance. BLOCK DIAGRAM CONNECTION DIAGRAM A1 A2 ADDRESS STORAGE CELL MATRIX ADDRESS 6 VCC (+5.0V) A3 DECODERS A4 ADDRESS 7 ADDRESS 0 64x16 64xl6 64x16 64x16 A5 ADDRESS B ADDRESS 1 ADDRESS 9 ADDRESS 2 DATA 1/0 1 ADDRESS 3 REF. ROW r--------, ~~----~--~~--~~ DATA 1/02 ADDRESS 4 A6 DATA 1/0 3 ADDRESS 5 A7 DATA 1/04 WRITE...