AmZ8166 Datasheet | AMD

DESCRIPTION The Am Z8165 and Am Z8166 are designed and specified to drive the capacitive input characteristics of the address and control lines of M08 dynamic RAMs. The unique design of the lower output driver includes a collector resistor to control undershoot on the HIGH-to-LOW transition. The upper output driver pulls up to Vcc - 1.15V to be patible with M08 memory and is designed to have a rise time symmetrical with the lower output's controlled fa!1 time. This allows optimization of Dynamic RAM performance. The Am Z8165 and Am Z8166 are pin-patible with the popular '8240 and '8244 with identical3-state output enable controls. The Am Z8165 has inverting drivers and the Am Z8166 has non-inverting drivers. The inclusion of an internal resistor in the lower output driver eliminates the requirement for an external series resistor, therefore reducing package count and the board area required. The internal resistor controls the output fall and undershoot without slowing the output rise. These devices are designed for use with the Am Z8164 Dynamic Memory Controller where large dynamic memories with highly capacitive input lines require additional buffering. Driving eight address lines or four RA8 and four CA8 lines with drivers on the same silicon chip also provides a significant performance advantage by minimizing skew between drivers. Each device has specified skew between drivers to improve the memory access worst case timing over the min and max tp D difference of unspecified devices. TYPICAL OUTPUT DRIVER ------1~--_o Vee R ",,30n OUTPUT TO + - - - - RAM ADDRESS OR CONTROL R ",,25n LINES BLI-212 l Al l A2 l A3 l A4 16 Note: Pin 1 is marked for orientation. BLI-210 l Yl 2Al Am Z8165 2Yl LOGIC DIAGRAMS 1Y2 2A2 2Y2 1Y3 2A3 l Y4 2A4 2G 2Y3 Inputs Outputs 2Y4 8-52 -----<1>----_0 GND BLI- 211 Am Z8166 2Yl BLI-...