DESCRIPTION
Logic Symbol Truth Table A AN4x B ABCDQ C Q HHHX L XXXHL D All other combinations H Core Logic HDL Syntax Verilog .................... AN4x inst_name (Q, A, B, C, D); VHDL...................... inst_name: AN4x port map (Q, A, B, C, D); Pin Loading Pin Name A B C D AN41 1.0 1.0 1.0 1.0 Equivalent Loads AN42 AN44 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 AN46 2.1 2.1 2.1 1.0 Size And Power Characteristics Size And Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) AN41 2.0 TBD 2.7 AN42 4.0 TBD 7.6 AN44 4.0 TBD 7.8 AN46 8.0 TBD 15.5 a. See page 2-15 for power equation. 3-13 $1 [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process AN41 Number of Equivalent Loads From: Any Input To: Q tPLH tPHL Number of
AMI
