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ANE2 - CMOS Gate Array

Description

ANEx is a family of AND-NOR circuits consisting of three 3-input AND gates into a 3-input NOR gate.

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Datasheet Details

Part number ANE2
Manufacturer AMI
File Size 30.02 KB
Description CMOS Gate Array
Datasheet download datasheet ANE2 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Core Logic $1([ $0,+*  PLFURQ &026 *DWH $UUD Description ANEx is a family of AND-NOR circuits consisting of three 3-input AND gates into a 3-input NOR gate. Logic Symbol Truth Table A ANEx B ABCDE FGH I Q C D HHHXXXXXX L E F Q XXXHHHXXX L G XXXXXXHHH L H I All other combinations H HDL Syntax Verilog .................... ANEx inst_name (Q, A, B, C, D, E, F, G, H, I); VHDL...................... inst_name: ANEx port map (Q, A, B, C, D, E, F, G, H, I); Pin Loading Pin Name A B C D E F G H I ANE2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads ANE4 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ANE6 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.
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