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DF001 - CMOS Gate Array

General Description

DF00x is a family of static, master-slave D flip-flops without SET or RESET.

Output is unbuffered and changes state on the rising edge of the clock.

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Datasheet Details

Part number DF001
Manufacturer AMI
File Size 29.56 KB
Description CMOS Gate Array
Datasheet download datasheet DF001 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Core Logic ')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF00x is a family of static, master-slave D flip-flops without SET or RESET. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol Truth Table DF00x DQ C DCQ H↑H L↑L X L NC NC = No Change HDL Syntax Verilog .................... DF00x inst_name (Q, C, D); VHDL...................... inst_name: DF00x port map (Q, C, D); Pin Loading Pin Name D C Equivalent Loads DF001 DF002 1.0 1.0 1.0 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF001 6.0 TBD 14.0 DF002 7.0 TBD 15.7 a. See page 2-15 for power equation.