DESCRIPTION
Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol Truth Table DF00x DQ C DCQ H↑H L↑L X L NC NC = No Change HDL Syntax Verilog .................... DF00x inst_name (Q, C, D); VHDL...................... inst_name: DF00x port map (Q, C, D); Pin Loading Pin Name D C Equivalent Loads DF001 DF002 1.0 1.0 1.0 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF001 6.0 TBD 14.0 DF002 7.0 TBD 15.7 a. See page 2-15 for power equation. 3-49 Core Logic ') [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 4 DF001 From: C To: Q tPLH tPHL 0.66 0.56 0.75 0.67 Number of Equivalent Loads 1 8 DF002 From: C To: Q tP
AMI
