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DF104 - CMOS Gate Array

Download the DF104 datasheet PDF. This datasheet also covers the DF101 variant, as both devices belong to the same cmos gate array family and are provided as variant models within a single manufacturer datasheet.

General Description

DF10x is a family of static, master-slave D flip-flops.

SET is asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DF101-AMI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number DF104
Manufacturer AMI
File Size 40.28 KB
Description CMOS Gate Array
Datasheet download datasheet DF104 Datasheet

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Other Datasheets by AMI

Part Number Description
DF101 CMOS Gate Array
DF102 CMOS Gate Array
DF106 CMOS Gate Array
DF111 CMOS Gate Array
DF112 CMOS Gate Array

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Core Logic ')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF10x is a family of static, master-slave D flip-flops. SET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol Truth Table DF10x DSQ C Q SN D C Q QN L XXH L HL ↑ LH HH ↑H L H X L NC NC NC = No Change HDL Syntax Verilog...................DF10x inst_name (Q, QN, C, D, SN); VHDL...................... inst_name: DF10x port map (Q, QN, C, D, SN); Pin Loading Pin Name D C SN DF101 1.0 1.0 2.1 Equivalent Loads DF102 DF104 1.0 1.0 1.0 1.0 2.1 3.2 DF106 1.0 1.0 3.2 Size And Power Characteristics Cell Equivalent Gates Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF101 8.0 TBD 17.8 DF102 9.0 TBD 21.0 DF104 13.0 TBD 32.