DESCRIPTION
RESET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol Truth Table DF11x DQ C RQ RN D C Q QN L XX LH HL ↑ LH HH ↑H L H X L NC NC NC = No Change HDL Syntax Verilog...................DF11x inst_name (Q, QN, C, D, RN); VHDL...................... inst_DF11x : DF11x port map (Q, QN, C, D, RN); Pin Loading Pin Name D C RN DF111 1.0 1.0 1.0 Equivalent Loads DF112 DF114 1.0 1.0 1.0 1.0 1.0 1.0 DF116 1.0 1.0 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF111 9.0 TBD 21.1 DF112 10.0 TBD 24.4 DF114 14.0 TBD 37.0 DF116 16.0 TBD 43.5 a. See page 2-15 for power equation. 3-60 ® Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 DF1
AMI
