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DF402 - CMOS Gate Array

Download the DF402 datasheet PDF. This datasheet also covers the DF401 variant, as both devices belong to the same cmos gate array family and are provided as variant models within a single manufacturer datasheet.

General Description

DF40x is a family of static, master-slave, multiplexed scan D flip-flops.

SET is asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DF401-AMI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number DF402
Manufacturer AMI
File Size 46.03 KB
Description CMOS Gate Array
Datasheet download datasheet DF402 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF40x is a family of static, master-slave, multiplexed scan D flip-flops. SET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF40x DS C SD SE Q Q Truth Table C D SD SE SN Q QN ↑HX LHHL ↑LXLHLH ↑ XHHHH L ↑X LHHLH XXXXLHL L X X X H NC NC NC = No Change Core Logic HDL Syntax Verilog .................... DF40x inst_name (Q, QN, C, D, SD, SE, SN); VHDL...................... inst_name: DF40x port map (Q, QN, C, D, SD, SE, SN); Pin Loading Pin Name C D SD SE SN DF401 1.0 1.0 1.0 2.1 2.1 Equivalent Loads DF402 DF404 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.2 2.1 3.1 DF406 1.0 1.0 1.0 2.2 3.