DESCRIPTION
SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF42x DS C SD SE R Q Q Truth Table C D RN SD SE SN Q QN ↑HHX LHHL ↑ L HX L H L H ↑ XHHHHH L ↑ XH L HH L H XX L XXH L H XXHXX L H L X X L X X L IL IL L X H X X H NC NC NC = No Change IL = Illegal Condition Core Logic HDL Syntax Verilog .................... DF421x inst_name (Q, QN, C, D, RN, SD, SE, SN); VHDL...................... inst_name: DF421x port map (Q, QN, C, D, RN, SD, SE, SN); Pin Loading Pin Name C D RN SD SE SN DF421 1.0 1.0 2.1 1.0 2.1 2.1 Equivalent Loads DF422 DF424 1.0 1.0 1.0 1.0 2.1 1.1 1.0 1.0 2.1 2.1 2.1 2.1 DF426 1.0 1.0 1.1 1.0 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF421 13.0 TBD 26.1
AMI
