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DF426 - CMOS Gate Array

Download the DF426 datasheet PDF. This datasheet also covers the DF421 variant, as both devices belong to the same cmos gate array family and are provided as variant models within a single manufacturer datasheet.

General Description

DF42x is a family of static, master-slave, multiplexed scan D flip-flops.

SET and RESET are asynchronous and active low.

Outputs are buffered and change state on the rising edge of the clock.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DF421-AMI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number DF426
Manufacturer AMI
File Size 49.59 KB
Description CMOS Gate Array
Datasheet download datasheet DF426 Datasheet

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Other Datasheets by AMI

Part Number Description
DF421 CMOS Gate Array
DF422 CMOS Gate Array
DF424 CMOS Gate Array
DF401 CMOS Gate Array
DF402 CMOS Gate Array

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
')[ ® $0,+*  PLFURQ &026 *DWH $UUD Description DF42x is a family of static, master-slave, multiplexed scan D flip-flops. SET and RESET are asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF42x DS C SD SE R Q Q Truth Table C D RN SD SE SN Q QN ↑HHX LHHL ↑ L HX L H L H ↑ XHHHHH L ↑ XH L HH L H XX L XXH L H XXHXX L H L X X L X X L IL IL L X H X X H NC NC NC = No Change IL = Illegal Condition Core Logic HDL Syntax Verilog .................... DF421x inst_name (Q, QN, C, D, RN, SD, SE, SN); VHDL...................... inst_name: DF421x port map (Q, QN, C, D, RN, SD, SE, SN); Pin Loading Pin Name C D RN SD SE SN DF421 1.0 1.0 2.1 1.0 2.1 2.1 Equivalent Loads DF422 DF424 1.0 1.0 1.0 1.0 2.1 1.1 1.0 1.0 2.1 2.