DESCRIPTION
RESET and SET are active low. Logic Symbol DL66x DSQ G Q R Truth Table SN RN D GN Q QN L L X X IL IL LHXXHL HLXXLH H H X H NC NC HHL L LH HHH L H L IL = Illegal NC = No Change HDL Syntax Verilog .................... DL66x inst_name (Q, QN, D, GN, RN, SN); VHDL...................... inst_name: DL66x port map (Q, QN, D, GN, RN, SN); Pin Loading Pin Name D GN SN RN DL661 1.0 1.0 1.0 1.0 Equivalent Loads DL662 DL664 1.0 1.0 1.0 1.0 1.0 2.1 1.0 1.0 DL666 1.0 1.0 2.1 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DL661 7.0 TBD 13.4 DL662 8.0 TBD 16.6 DL664 13.0 TBD 34.0 DL666 15.0 TBD 40.5 a. See page 2-15 for power equation. 3-114 Core Logic ® Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical
AMI
