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Core Logic
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Description EO3x is a family of 3-input gates which perform the logical exclusive OR (XOR) function.
Logic Symbol
EO3x A B C
Truth Table A B CQ LLLL L LHH
Q LHLH L HH L HL LH HLHL HHL L HHHH
HDL Syntax Verilog .................... EO3x inst_name (Q, A, B, C); VHDL...................... inst_name: EO3x port map (Q, A, B, C);
Pin Loading
Pin Name
A B C
EO31 2.1 2.1 2.1
EO32 2.1 2.1 3.4
Equivalent Loads EO33 2.1 2.1 3.2
EO34 2.1 2.1 3.2
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
EO31
5.0
TBD
10.6
EO32
8.0
TBD
15.2
EO33
8.0
TBD
16.9
EO34
10.0
TBD
19.7
EO36
10.0
TBD
22.4
a. See page 2-15 for power equation.
3-122
EO36 2.1 2.1 3.
EO34 Datasheet
