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JK011 - CMOS Gate Array

Description

JK01x is a family of static, master-slave JK flip-flops.

RESET is asynchronous and active low.

Output is unbuffered and changes state on the rising edge of the clock.

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Datasheet Details

Part number JK011
Manufacturer AMI
File Size 38.21 KB
Description CMOS Gate Array
Datasheet download datasheet JK011 Datasheet
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Core Logic -.[ ® $0,+*  PLFURQ &026 *DWH $UUD Description JK01x is a family of static, master-slave JK flip-flops. RESET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol JK01x JQ C K R Truth Table RN J K C Q(n+1) LXXX L HL L ↑ NC HLH↑ L HHL ↑ H H H H ↑ Q(n) NC = No Change HDL Syntax Verilog .................... JK01x inst_name (Q, C, J, K, RN); VHDL...................... inst_name: JK01x port map (Q, C, J, K, RN); Pin Loading Pin Name J K C RN Equivalent Loads JK011 JK012 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) JK011 11.0 TBD 25.0 JK012 12.0 TBD 28.3 a.
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