DESCRIPTION
RESET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol JK01x JQ C K R Truth Table RN J K C Q(n+1) LXXX L HL L ↑ NC HLH↑ L HHL ↑ H H H H ↑ Q(n) NC = No Change HDL Syntax Verilog .................... JK01x inst_name (Q, C, J, K, RN); VHDL...................... inst_name: JK01x port map (Q, C, J, K, RN); Pin Loading Pin Name J K C RN Equivalent Loads JK011 JK012 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) JK011 11.0 TBD 25.0 JK012 12.0 TBD 28.3 a. See page 2-15 for power equation. 3-137 Core Logic -. [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1
AMI
