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Description
ODCHXE24 is a high performance, 24 mA, non-inverting, CMOS-level, tristate output buffer piece with active low enable.
Logic Symbol
Truth Table
Pin Loading
ODCHXE24 EN A
PADM
EN A PADM
LL
L
LH H
HX
Z
A EN PADM
Load 3.5 eql 6.5 eql 4.93 pF
HDL Syntax Verilog .................... ODCHXE24 inst_name (PADM, A, EN); VHDL...................... inst_name: ODCHXE24 port map (PADM, A, EN);
Power Characteristics
Parameter Static IDD (TJ = 85°C) EQLpd
See page 2-15 for power equation.
Value TBD 297.0
Units nA Eq-load
Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
Delay (ns) From
To Parameter
15
A
PADM
tPLH tPHL
1.00 0.57
tHZ 1.06
EN
PADM
tLZ tZH
1.02 0.86
tZL 0.
ODCHXE24 Datasheet
