DESCRIPTION
Logic Symbol Truth Table Pin Loading ODCHXE24 EN A PADM EN A PADM LL L LH H HX Z A EN PADM Load 3.5 eql 6.5 eql 4.93 pF HDL Syntax Verilog .................... ODCHXE24 inst_name (PADM, A, EN); VHDL...................... inst_name: ODCHXE24 port map (PADM, A, EN); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 297.0 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Delay (ns) From To Parameter 15 A PADM tPLH tPHL 1.00 0.57 tHZ 1.06 EN PADM tLZ tZH 1.02 0.86 tZL 0.99 Delay will vary with input conditions. See page 2-17 for interconnect estimates. 50 1.46 1.38 1.33 1.35 Capacitive Load (pF) 100 2.10 1.82 2.00 1.78 200 3.41 2.65 3.33 2.63 300 (max) 4.76 3.55 4.65 3.53 Pad Logic 4-
AMI