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ODCXIP02 - CMOS Gate Array

This page provides the datasheet information for the ODCXIP02, a member of the ODCXIP01 CMOS Gate Array family.

Datasheet Summary

Description

ODCXIPxx is a family of 1 to 8 mA, inverting, CMOS-level, output buffer pieces with P-channel, open-drains (pull-up).

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Datasheet preview – ODCXIP02

Datasheet Details

Part number ODCXIP02
Manufacturer AMI
File Size 24.25 KB
Description CMOS Gate Array
Datasheet download datasheet ODCXIP02 Datasheet
Additional preview pages of the ODCXIP02 datasheet.

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2'&;,3[[ ® $0,+*  PLFURQ &026 *DWH $UUD Description ODCXIPxx is a family of 1 to 8 mA, inverting, CMOS-level, output buffer pieces with P-channel, open-drains (pull-up). Logic Symbol Truth Table ODCXIPxx A PADM A PADM LH HZ Z = High Impedance HDL Syntax Verilog .................... ODCXIPxx inst_name (PADM, A); VHDL...................... inst_name: ODCXIPxx port map (PADM, A); Pin Loading Pin Name A (eq-load) PADM (pF) ODCXIP01 2.8 4.92 Load ODCXIP02 ODCXIP04 2.8 2.8 4.92 4.92 ODCXIP08 3.9 4.93 Power Characteristics Cell Output Drive (mA) ODCXIP01 1 ODCXIP02 2 ODCXIP04 4 ODCXIP08 8 a. See page 2-15 for power equation. Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TBD 148.8 TBD 153.6 TBD 162.0 TBD 178.
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