DESCRIPTION
Logic Symbol Truth Table ODTXXNxx A PADM A PADM LL HZ Z = High Impedance HDL Syntax Verilog .................... ODTXXNxx inst_name (PADM, A); VHDL...................... inst_name: ODTXXNxx port map (PADM, A); Pin Loading Pin Name A (eq-load) PADM (pF) ODTXXN01 4.3 4.90 ODTXXN02 4.3 4.90 ODTXXN04 4.3 4.91 Load ODTXXN08 8.3 4.90 ODTXXN12 8.3 4.91 Power Characteristics Cell Output Drive (mA) ODTXXN01 ODTXXN02 ODTXXN04 ODTXXN08 ODTXXN12 ODTXXN16 ODTXXN24 1 2 4 8 12 16 24 a. See page 2-15 for power equation. Power Characteristicsa Static IDD (TJ = 85°C) (nA) TBD EQLpd (Eq-load) 141.7 TBD 143.5 TBD 147.6 TBD 156.9 TBD 163.7 TBD 173.1 TBD 184.9 ODTXXN16 8.3 4.91 ODTXXN24 8.3 4.91 Pad Logic 4-47 2'7;;1[[ ® $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditi
AMI
