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$0,+* PLFURQ &026 *DWH $UUD
Description ON6x is a family of OR-NAND circuits consisting of two 3-input OR gates into a 2-input NAND gate.
Logic Symbol
Truth Table
A
ON6x
A BCDE FQ
B L L LXXXH
C Q XXXL L LH
D
All other combinations
L
E
F
Core Logic
HDL Syntax Verilog .................... ON6x inst_name (Q, A, B, C, D, E, F); VHDL...................... inst_name: ON6x port map (Q, A, B, C, D, E, F);
Pin Loading
Pin Name
A B C D E F
ON62 1.0 1.0 1.0 1.0 1.0 1.0
Equivalent Loads ON64 1.0 1.0 1.0 1.0 1.0 1.0
ON66 2.1 2.1 2.1 2.1 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
ON62
5.0
TBD
9.2
ON64
6.0
TBD
9.8
ON66
12.0
TBD
17.0
a. See page 2-15 for power equation.
ON62 Datasheet
