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Description ONAx is a family of OR-NAND circuits consisting of two 3-input OR gates into a 3-input NAND gate.
Logic Symbol
Truth Table
A
ONAx
A BCDE FGQ
B L L LXXXXH
C
XXXL L LXH
D
E Q XXXXXXLH
F
All other combinations
L
G
Core Logic
HDL Syntax Verilog .................... ONAx inst_name (Q, A, B, C, D, E, F, G); VHDL...................... inst_name: ONAx port map (Q, A, B, C, D, E, F, G;)
Pin Loading
Pin Name
A B C D E F G
ONA2 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Equivalent Loads ONA4 1.0 1.0 1.0 1.0 1.0 1.0 1.0
ONA6 2.1 2.1 2.1 2.1 2.1 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
ONA2
6.0
TBD
11.7
ONA4
8.0
TBD
12.3
ONA6
12.0
TBD
22.
ONA2 Datasheet
