Datasheet Summary
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Description ONAx is a family of OR-NAND circuits consisting of two 3-input OR gates into a 3-input NAND gate.
Logic Symbol
Truth Table
ONAx
A BCDE FGQ
B L L LXXXXH
XXXL L LXH
E Q XXXXXXLH
All other binations
Core Logic
HDL Syntax Verilog .................... ONAx inst_name (Q, A, B, C, D, E, F, G); VHDL...................... inst_name: ONAx port map (Q, A, B, C, D, E, F, G;)
Pin Loading
Pin Name
A B C D E F G
ONA2 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Equivalent Loads ONA4 1.0 1.0 1.0 1.0 1.0 1.0 1.0
ONA6 2.1 2.1 2.1 2.1 2.1 2.1 2.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ =...