A65H83181 Datasheet | AMIC Technology

A65H73361/A65H83181 Series Preliminary Document Title 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Revision History Rev. No. History Add JTAG standard Issue Date February 12, 1999 Remark Preliminary PRELIMINARY (February, 1999, Version 2.0) AMIC Technology, Inc. A65H73361/A65H83181 Series Preliminary Features n n n n 128K x 36 & 256K x 18 Late Write Synchronous Fast SRAM with Pipelined Data Output Fast access times: 2.5/3.0/3.5ns 128k x 36 or 256k x 18 organizations CMOS technology Register to register synchronous operation with selftimed late write n Single +3.3V ±5% power supply n Individual byte write and global write n n n n n n n HSTL input & output levels Boundary scan(JTAG) IEEE 1149.1 patible Asynchronous output enable Sleep mode (ZZ) Programmable impedance output drivers JEDEC Standard pinout and boundary scan order 7 x 17 bump plastic ball grid array (PBGA) package General Description The A65H73361 and A65H83181 are 128k words by 36 bits and 256k words by 18 bits late write synchronous 4Mb SRAMS built using high performance CMOS process. The differential clock are used to control the timing of read/write operation and all internal operations are selftimed. The positive edge triggered CK clock input controls all addresses write-enables and Synchronous select and data ins are registered. The data outs are controlled by the output registers off the next positive clock edge to be updated. The internal write buffer enables write data to be accepted on the rising edge of the clock one cycle after address and control signals. The SRAM uses HSTL I/O interfaces with programmable impedance output drivers allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. PRELIMINARY (February, 1999, Version 2.0) AMIC Technology, Inc. A65H73361/A65H83181 Series Pin Configuration A65H73361...