A67L73321 - 256K X 16/18/ 128K X 32/36 LVTTL/ Flow-through DBA SRAM

The AMIC Direct Bus Alternation™ (DBA™) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

• n Fast access time: 10/11/12 ns (100, 90, 83 MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal +3.3V ± 5% power supply n Individual Byte Write control capability n Clock enable ( CEN ) pin to enable clock and suspend operations n Clock-controlled and registered address, data and control signals n Registered output for pipelined.