A67L06181 Datasheet | AMIC Technology

A67L06181/A67L93361 Preliminary Document Title 1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM Revision History Rev. No. 1M X 18, 512K X 36 LVTTL, Flow-through ZeBLTM SRAM History Initial issue Issue Date August, 20, 2005 Remark Preliminary PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. A67L06181/A67L93361 Preliminary Features Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals...