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A67L9336 - (A67L0618 / A67L9336) Pipelined ZeBL SRAM

This page provides the datasheet information for the A67L9336, a member of the A67L0618 (A67L0618 / A67L9336) Pipelined ZeBL SRAM family.

Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67L0618, A67L9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.

Features

  • Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined.

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Datasheet Details

Part number A67L9336
Manufacturer AMIC Technology
File Size 252.34 KB
Description (A67L0618 / A67L9336) Pipelined ZeBL SRAM
Datasheet download datasheet A67L9336 Datasheet
Additional preview pages of the A67L9336 datasheet.

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Other Datasheets by AMIC Technology
  • A67L93361 - (A67L06181 / A67L93361) Flow-through ZeBL SRAM
  • A67L9318 - 512K X 18- 256K X 36 LVTTL / Pipelined ZeBL SRAM
  • A67L93181 - 512K X 18- 256K X 36 LVTTL / Flow-through ZeBL SRAM
  • A67L0618 - Pipelined ZeBL SRAM
  • A67L06181 - Flow-through ZeBL SRAM
  • A67L0636 - 2M X 18- 1M X 36 LVTTL Pipelined ZeBL SRAM
  • A67L1618 - 2M X 18- 1M X 36 LVTTL Pipelined ZeBL SRAM
  • A67L7332 - 256K X 16/18/ 128K X 32/36 LVTTL/ Pipelined DBA SRAM

Full PDF Text Transcription

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A67L0618/A67L9336 Preliminary Document Title 1M X 18, 512K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 1M X 18, 512K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date August, 20, 2005 Remark Preliminary PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. A67L0618/A67L9336 Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.
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