A67P1618A Overview
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P1618A, A67P0636A SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.
A67P1618A Key Features
- Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz)
- Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization
- Signal +2.5V ± 5% power supply
- Individual Byte Write control capability
- Clock enable ( CEN) pin to enable clock and suspend
- Clock-controlled and registered address, data and
- Registered output for pipelined