FEATURES
n Power supply range: 2.7V to 3.3V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating: 55ns: 25mA (max.) 70ns: 20mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (min.) n Available in 32-pin SOP, TSOP, TSSOP (8X13.4mm) and 36-pin CSP packages 256K X 8 BIT LOW VOLTAGE CMOS SRAM GENERAL DESCRIPTION
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2V. Product Family Product Family Operating Temperature VCC Range Power Dissipation Speed Data Retention (ICCDR, Typ.) 0.5µA Standby (ISB1, Typ.) 0.5µA Operating (ICC2, Typ.) 3mA Package Type 32L SOP 32L TSOP 32L TSSOP 36L CSP LP62S2048A -40°C ~ +85°C 2.7V~3.3V 55ns / 70ns 1.