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LP62S2048A-I - 256K X 8 BIT LOW VOLTAGE CMOS SRAM

General Description

The LP62S2048A-I is a low operating current 2,097,152-bit static random access memory organized as 262,144 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V.

It is built using AMIC's high performance CMOS process.

Key Features

  • n Power supply range: 2.7V to 3.3V n Access times: 55/70 ns (max. ) n Current: Very low power version: Operating: 55ns: 25mA (max. ) 70ns: 20mA (max. ) Standby: 10µA (max. ) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy.

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Datasheet Details

Part number LP62S2048A-I
Manufacturer AMIC Technology
File Size 190.83 KB
Description 256K X 8 BIT LOW VOLTAGE CMOS SRAM
Datasheet download datasheet LP62S2048A-I Datasheet

Full PDF Text Transcription for LP62S2048A-I (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for LP62S2048A-I. For precise diagrams, and layout, please refer to the original PDF.

LP62S2048A-I Series Preliminary Document Title 256K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 256K X 8 BIT LOW VOLTAGE CMOS SRAM History Initial issue I...

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ev. No. 0.0 256K X 8 BIT LOW VOLTAGE CMOS SRAM History Initial issue Issue Date June 24, 2002 Remark Preliminary PRELIMINARY (June, 2002, Version 0.0) 1 AMIC Technology, Inc. LP62S2048A-I Series Preliminary Features n Power supply range: 2.7V to 3.3V n Access times: 55/70 ns (max.) n Current: Very low power version: Operating: 55ns: 25mA (max.) 70ns: 20mA (max.) Standby: 10µA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL-compatible n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2V (mi

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