Datasheet Summary
Features
- 80C51 Core Architecture
- 256 Bytes of On-chip RAM
- 1 KB of On-chip XRAM
- 32 KB of On-chip Flash Memory
- Data Retention: 10 Years at 85°C Read/Write Cycle: 10K
- 2 KB of On-chip Flash for Bootloader
- 2 KB of On-chip EEPROM
Read/Write Cycle: 100K
- 14-sources 4-level Interrupts
- Three 16-bit Timers/Counters
- Full Duplex UART patible 80C51
- Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz)
- Five Ports: 32 + 2 Digital I/O Lines
- Five-channel 16-bit PCA with:
- PWM (8-bit)
- High-speed Output
- Timer and Edge Capture
- Double Data Pointer
- 21-bit Watchdog Timer (7 Programmable Bits)
- 10-bit Resolution Analog to Digital Converter (ADC) with 8...