Datasheet Summary
Features
- 80C52 patible
- 8051 Instruction patible
- Four 8-bit I/O Ports (44 Pins Version)
- Three 16-bit Timer/Counters
- 256 bytes Scratch Pad RAM
- 11 Interrupt Sources With 4 Priority Levels
- ISP (In-System Programming) Using Standard VCC Power Supply
- Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
- Boot ROM Contains Serial Loader for In-System Programming
- High-speed Architecture
- In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
- In X2 Mode (6 Clocks/Machine Cycle)
20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
30 MHz (Vcc 4.5V to...