Datasheet Summary
Features
General
- -
- -
- -
- High-performance, Low-power secureAVR ™ Enhanced RISC Architecture
- 135 Powerful Instructions (Most Executed in a Single Clock Cycle) Low Power Idle and Power-down Modes Bond Pad Locations Conforming to ISO 7816-2 ESD Protection to ± 4000V Operating Ranges: 1.62 to 5.50V pliant with GSM, 3GPP and EMV 2000 Specifications, PC Industry patible Available in Wafers, Modules, and Industry-standard Packages
Memory
- 192K Bytes of ROM Program Memory
- 36K Bytes of EEPROM, Including 128 OTP Bytes and 384-byte Bit-addressable Bytes
- 1 to 128-byte Program / Erase
- 1ms Program / 1ms Erase
- Typically 500,000 Write/Erase Cycles at a Temperature of 25 oC
- 10...